Recently, a demand for liquid crystal display devices for use in large-screen liquid crystal TV sets as well as for use in portable telephones (such as mobile phones or cellular phones), notebook PCs, and monitors has expanded. As these liquid crystal display devices, an active matrix driving liquid crystal display device capable of performing high-definition display is employed. First, referring to FIG. 11, a typical configuration of the active matrix driving liquid crystal display device will be outlined. FIG. 11 schematically shows a main configuration connected to a pixel in a liquid crystal display unit, using an equivalent circuit.
Generally, a display unit 960 of the active matrix driving liquid crystal display device includes a semiconductor substrate, an opposing substrate, and a liquid crystal sealed in between these two substrates by opposing these two substrates. On the semiconductor substrate, transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 are arranged in a matrix form (of 1280×3 pixel rows×1024 pixel columns in the case of a color SXGA panel, for example). One transparent electrode 967 is formed on an entire surface of the opposing substrate.
A TFT 963 having a switching function is on/off-controlled by a scan signal. When the TFT 963 is turned on, a gray scale signal voltage corresponding to a video data signal is applied to a pixel electrode 964. Transmittance of the liquid crystal is changed by a potential difference between each pixel electrode 964 and the opposing substrate electrode 967, and even after the TFT 963 has been turned off, the potential difference is held by a liquid crystal capacitance 965 and an auxiliary capacitance 966 for a certain period, thereby displaying an image.
On the semiconductor substrate, data lines 962 and scan lines 961 are wired in the form of grids (in which 1280×3 data lines and 1024 scan lines are arranged in the case of the color SXGA panel). A data line 962 sends a plurality of level voltages (gray scale signal voltages) applied to each pixel electrode 964, and a scan line 961 sends the scan signal. Due to a capacitance produced at an intersection between each of the scan lines 961 and each of the data lines 962 and a liquid crystal capacitance sandwiched between the semiconductor substrate and the opposing substrate, the scan lines 961 and the data lines 962 have become a large capacitive load.
The scan signal is supplied to a scan line 961 from a gate driver 970, and a gray scale signal voltage is supplied to each pixel electrode 964 from a data driver 980 through a data line 962. The gate driver 970 and the data driver 980 are controlled by a display controller 950. A clock CLK, a control signal, and a voltage supply that are necessary are supplied from the display controller 950 to each of the gate driver 970 and the data driver 980, and video data is supplied to the data driver 980. Currently, digital data has been predominantly used as the video data.
Rewriting of data of one screen is performed in one frame period (of approximately 0.017 seconds, usually). Data is successively selected every pixel row (every line) by each scan line, and a gray scale voltage signal is supplied from each data line within a selection period.
While it suffices for the gate driver 970 to supply at least the scan signal of a binary value, the data driver 980 needs to drive a data line by the gray scale voltage signal of multi-valued levels according to the number of gray scales. For this reason, the data driver 980 includes a decoder that converts the video data to an analog voltage and a digital-to-analog converter circuit (DAC) formed of an operational amplifier that amplifies the analog voltage and outputs the amplified analog voltage to a corresponding data line 962.
Recently, liquid crystal display devices have become larger in size and the number of colors (gray scales) used in the liquid crystal display devices has also increased. In a liquid crystal TV, approximately 16,800 thousand colors (video data of eight bits for each of colors R, G, B) to ten hundred of million colors (video data of ten bits for each of the colors R, G, B) are demanded. Among data drivers that implement the increase in the number of gray scales described above, some of the data drivers including a DAC that outputs a linear voltage (hereinafter written as a linear DAC) of bits larger than the number of bits that can be displayed by the liquid crystal display device (in which the number of gray scales being equal to 2 to the power of the number of bits) by two to three bits is being on the market. While a commonly used DAC of the data driver has a nonlinear gray scale-voltage characteristic due to a gamma characteristic of the liquid crystal, the linear DAC has a linear gray scale-voltage characteristic in which the number of gray scales is four to eight times the number of gray scales of the usual data driver. By assigning a gray scale suited to the gamma characteristic from among a great number of linear output levels, display can be implemented. For this reason, the data driver including the linear DAC has a data conversion circuit that converts bit data (such as 10-bit data) of an image source to bit data (such as 12-bit data) of the linear DAC according to the gamma characteristic of the liquid crystal and can accommodate a different liquid crystal gamma characteristic just by changing a conversion table. The data driver including the linear DAC thus can be used as a general-purpose driver.
However, there is a problem that the circuit size of the DAC will increase due to an increase in the number of bits, and the chip area of a data driver LSI will be thereby increased, which results in a high cost. In conventional DACs, it is a common practice to select one voltage corresponding to video data by a decoder from among reference voltages the number of which is the same as the number of gray scales for display and to amplify the selected voltage by a voltage follower circuit (not shown). When video data is increased in bit width from eight bits to 10 bits, for example, the number of the reference voltages becomes four times, and the circuit size becomes four times or larger. When the linear DAC is employed, the circuit size is further increased to be four to eight times the circuit size of a conventional DAC.
Some configurations for restricting an increase in the area of the DAC against an increase in the number of bits have been already proposed. In each of Patent Documents 1 and 2, which will be listed later, there is proposed a DAC configuration for a display device in which using an operational amplifier that interpolates (internally divides) two reference voltages at a predetermined ratio, the number of reference voltages to be input to a DAC is reduced to a half or one quarter of the number of gray scales for display, thereby reducing the area of the DAC. In Patent Document 3, which will be listed later, there is proposed a configuration that greatly reduces the area of a DAC as an interpolating DAC. The DAC configuration in each of Patent Documents 1 and 2 is based on the configuration in Patent Document 3. In Patent Document 4, which will be listed later, there is proposed a DAC configuration aimed at improvement of an output voltage accuracy of the interpolating DAC. The same basic principle for saving the DAC area is used in Patent Documents 1 to 4. Patent Document 4, which will be listed later, will be described below as a representative of the configurations for restricting an increase in the DAC area.
FIG. 12 is a diagram showing the DAC configuration proposed in Patent Document 4. Referring to FIG. 12, this DAC includes a resistor string 93 and a decoder 92. The resistor string 93 outputs first through (m+1)th reference voltages VR0 to VRm that have mutually different potentials from first through (m+1)th taps thereof, respectively. The decoder 92 receives the (m+1) reference voltages VR0 to VRm, selects adjacent two reference voltages according to an input data signal, and outputs one of the selected two reference voltages to each of first to fourth decoder output terminals. The decoder 92 is constituted from a first group, a second group, and a third group of switches. The first group of switches is constituted from m switches S1a to Sma. In each of the switches S1a to Sma, a first terminal is connected to a tap for a corresponding one of the m reference voltages VR0 to VR(m−1). Second terminals of the switches S1a to Sma are coupled together. The first group of switches selects one reference voltage Va from among the m reference voltages VR0 to VR(m−1) and outputs the selected one reference voltage Va to a second terminal of each of the m switches S1a to Sma. The second terminals of the m switches S1a to Sma constitute the first decoder output terminal. The second group of switches is constituted from m switches S1b to Smb. In each of the switches S1b to Smb, a first terminal is connected to a tap for a corresponding one of m reference voltages VR1 to VRm. Second terminals of the switches S1b to Smb are coupled together. The second group of switches selects a higher level reference voltage Vb adjacent to the reference voltage Va. The third group of switches is constituted from selector switches SW1, SW2, and SW3 each of which controls connection between one of the second terminals of the first group of switches and the second terminals of the second group of switches and a corresponding one of the second to fourth decoder output terminals. The third group of switches selects one of the reference voltages Va and Vb and supplies the selected voltage to the second to fourth decoder output terminals, respectively. The DAC in FIG. 12 further includes an amplifying circuit 91 that receives outputs of the first to fourth decoder output terminals.
The amplifying circuit 91 includes four differential pairs (Q0A, Q0B), (Q1A, Q1B), (Q2A, Q2B), and (Q3A, Q3B), each of which is driven by an individual current source. Output pairs of the four differential pairs (Q0A, Q0B), (Q1A, Q1B), (Q2A, Q2B), and (Q3A, Q3B) are connected in common to input and output pairs of a current mirror circuit (QL1, QL2). Further, output signals of the four differential pairs (Q0A, Q0B), (Q1A, Q1B), (Q2A, Q2B), and (Q3A, Q3B) are differentially input to a differential amplifier 901 to output an output voltage Vout to an output terminal.
One (a second input) of an input pair of each of the four differential pairs (Q0A, Q0B), (Q1A, Q1B), (Q2A, Q2B) and (Q3A, Q3B) is connected in common to the output terminal, thereby forming a feedback configuration.
With respect to the other (a first input) of an input pair of each of the four differential pairs (Q0A, Q0B), (Q1A, Q1B), (Q2A, Q2B), and (Q3A, Q3B), the first input (a gate of a transistor Q0A) of the differential pair (Q0A, Q0B) is connected to the first decoder output terminal from which the reference voltage Va is output. First inputs (gates of transistors Q1A, Q2A, and Q3A) of the remaining three differential pairs (Q1A, Q1B), (Q2A, Q2B), and (Q3A, Q3B) are respectively connected to the second to fourth decoder output terminals from which one of the reference voltages Va and Vb is output, respectively.
The DAC in FIG. 12 generally operates as follows.
First, using an output of an MSB (Most Significant Bit) subword decoder 94 based on higher-order bit signals of input data, the kth switches (Ska and Skb) of the first and second groups of switches (S1a, . . . Sma) and (S1b, . . . Smb) are turned on, thereby selecting reference voltages at adjacent taps as the reference voltages Va and Vb. Then, by an output of an LSB (Least Significant Bit) subword decoder 95 based on lower-order bit signals of the input data, switching of the third group of switches (SW1, SW2, SW3) is further controlled.
According to a selecting condition in the third switches (SW1, SW2, SW3), one of four level voltages obtained by internally dividing the reference voltages Va and Vb at one of different ratios 0:1 (determined when the switches SW1, SW2, and SW3 all select the reference voltage Va), 1:3 (determined when one of the switches SW1, SW2, and SW3 selects the reference voltage Vb, and the other two switches select the reference voltage Va), 1:1 (determined when two of the switches SW1, SW2, and SW3 select the reference voltage Vb, and the other one switch selects the reference voltage Va), and 3:1 (determined when the switches SW1, SW2, and SW3 all select the reference voltage Vb) is output to the output terminal.
It is known from Patent Document 5, which will be listed later, that the output voltage of the amplifying circuit 91 has a characteristic of assuming an average value of voltages V0A, V1A, V2A, and V3A input to the gates of the transistors Q0A, Q1A, Q2A, and Q3A, respectively, or Vout=(V0A+V1A+V2A+V3A)/4. The operation described above is therefore evident from this fact.
In order to linearly output the four level voltages with a high voltage accuracy, it is necessary that the four differential pairs (Q0A, Q0B), (Q1A, Q1B), (Q2A, Q2B), and (Q3A, Q3B) should be formed of the transistors of the same size and that currents from the current sources for driving the four differential pairs respectively should also be controlled to be equivalent.
By the configuration and switch control as described above, the DAC in FIG. 12 can output a total of 4 m level voltages using the MSB and LSB subword decoders. When the number of the differential pairs in the amplifying circuit 91 is set to n, the DAC in FIG. 12 can output n×m level voltages to the output terminal.
When this principle on the DAC is used, the circuit size of the DAC or the area of the DAC can be greatly reduced, even if the number of bits of video data for the liquid crystal display device is greatly increased.
Other configurations for reducing the area of a DAC are proposed in Patent Document 6, which will be listed later. The configurations in Patent Document 6 are the configurations in each of which by employing an amplifying circuit having an amplification factor thereof being larger than one, a decoder is formed of a low voltage circuit, thereby reducing the area of the DAC. FIGS. 13A and 13B and FIGS. 14A and 14B are diagrams and graphs respectively showing configurations of amplifying circuits proposed in Patent Document 6 and input and output characteristics of the amplifying circuits.
FIG. 13A shows a configuration of a generally known non-inverting amplifying circuit. A voltage Vin is input to a non-inverting input terminal (+) of an amplifier 910, and an inverting input terminal (−) is connected to a connecting point between resistances Rfa and R1A connected in series between an output terminal Vout and a reference voltage supply GND. An output voltage Vout is given as follows:Vout=Vin×(1+RfA/R1A).The amplifier 910 can therefore output a voltage with the voltage amplification factor thereof being larger than one, according to a resistance ratio between the references RfA and R1A.
FIG. 13B is a graph showing the input-output characteristic in dot inversion driving when the non-inverting amplifying circuit in FIG. 13A is employed. Currently, the dot inversion driving scheme with high-image-quality driving is adopted in almost all large-sized liquid crystal display devices. In the dot inversion driving scheme, a voltage VCOM of an opposing substrate electrode of a liquid crystal panel is made constant, so that a data driver needs to output gray scale voltages of both of positive and negative polarities for the voltage VCOM. Accordingly, an output circuit of the data driver of the dot inversion driving, is provided with at least two voltage supplies having a potential difference that is approximately two times the maximum value of a liquid crystal application voltage (which is a potential difference between a gray scale voltage and the voltage VCOM). When negative and positive polarity voltage-gray scale characteristics to be output from the amplifier 910 in FIG. 13B are indicated by L93 and L94, respectively, the input voltage Vin can be reduced by setting the voltage amplification factor of each of the positive-polarity and negative-polarity voltage-gray scale characteristics based on the resistance ratio between the resistances RfA and R1A. More specifically, when voltage-gray scale characteristics input to the amplifier 910 are indicated by L91 and L92, the decoder that selects an input signal to the amplifier 910 can be formed of the low voltage circuit. With this arrangement, even if the number of devices that form the decoder remains unchanged, the area of the DAC can be reduced by reducing the size of each transistor.
FIG. 14A shows a configuration different from the configuration in FIG. 13A, which is the configuration of an amplifying circuit in which switching between an inverting amplifier and a voltage follower can be made by switch control.
When each of selector switches SW1, SW2, SW3, and SW4 is connected to a switching terminal 1, a voltage VE is input to a non-inverting input terminal (+) of an amplifier 920, and an inverting input terminal (−) is connected to a connecting point between a resistance RfB and a resistance R1B connected in series between an output terminal Vout and an input terminal to which a voltage Vin is supplied.
An output voltage Vout in this case becomes as follows:
                                 Vout          =                    ⁢                      VE            -                                          (                                                      RfB                    /                    R                                    ⁢                                                                          ⁢                  1                  ⁢                  B                                )                            ×                              (                                  Vin                  -                  VE                                )                                                                                  =                    ⁢                      VE            +                                          (                                                      RfB                    /                    R                                    ⁢                                                                          ⁢                  1                  ⁢                  B                                )                            ×                              (                                  VE                  -                  Vin                                )                                                        The amplifier 920 thus can output a voltage with the voltage amplification factor thereof being larger one, according to a resistance ratio between the resistance RfB and the resistance R1B.
On the other hand, when each of the selector switches SW1, SW2, SW3, and SW4 is connected to a switching terminal 2, the voltage Vin is input to the non-inverting input terminal (+) of the amplifier 920, and the inverting input terminal (−) is connected to the output terminal Vout. The output voltage Vout in this case becomes as follows:Vout=Vin
FIG. 14B is a graph showing the input and output characteristics in the dot inversion driving when the amplifying circuit in FIG. 14A is employed. When negative-polarity and positive-polarity voltage-gray scale characteristics to be output from the amplifier 920 in FIG. 14B are indicated by L95 and L96, respectively, the input voltage Vin can be reduced by setting the voltage amplification factor of the positive-polarity voltage-gray scale characteristic based on the resistance ratio between the resistances RfB and R1B. More specifically, when an input voltage-gray scale characteristic of the amplifier 920 is indicated by L94, the decoder that selects an input signal to the amplifier 920 can be formed of the low voltage circuit. With this arrangement, even if the number of devices that form the decoder remains unchanged, the area of the DAC can be reduced by reducing the size of each device. Incidentally, when gamma characteristics of the negative-polarity voltage-gray scale characteristic L95 and the positive-polarity voltage-gray scale characteristic L96 are different according to the polarity, the input voltage-gray scale characteristic of the amplifier 920 differs according to the polarity.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2000-183747A (FIGS. 1 and 2)
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2002-43944A (FIGS. 1 and 2)
[Patent Document 3]
U.S. Pat. No. 5,396,245 (FIG. 5)
[Patent Document 4]
U.S. Pat. No. 6,246,351 (FIG. 2)
[Patent Document 5]
U.S. Pat. No. 4,978,959 (Seventh Paragraph)
[Patent Document 6]
Japanese Patent Kokai Publication No. JP-A-11-184444 (FIGS. 1 and 4)